Test System Arms OLCF with Experimental Technology
Early development system to help researchers explore a possible HPC technology
The Oak Ridge Leadership Computing Facility (OLCF) is now equipped with ARM1, a new test bed for the ARM architecture and its power-efficient processors.
As an early development system, ARM1 gives researchers the opportunity to test various software packages and explore an experimental environment for ARM architecture–based systems. Because ARM processors differ from traditional supercomputing processors like Intel x86 and IBM POWER, their capacity for high-performance computing (HPC) applications has yet to be fully explored.
ARM Holdings, the company that designs the ARM technology, does not design processor chips bur rather licenses the ARM instruction set—the directions that tell the processors what to do. The licensees—the chip vendors—may then implement ARM into their own processors. Because ARM processors contain a simple instruction set and tend to be lower power, they are currently employed in smartphones, tablets, and laptops. The OLCF, home to the leadership-class Cray XK7 Titan supercomputer, is currently interested in ARM architectures because they may be a viable alternative to traditional architectures. The OLCF is a US Department of Energy (DOE) Office of Science User Facility located at DOE’s Oak Ridge National Laboratory.
“We’re always interested in new architectures, and in the last couple of years the ARM architecture has started to show real promise,” said Ross Miller, systems integration programmer in the Technology Integration Group at the OLCF. “Manufacturers are starting to produce processors designed for use in servers rather than in battery-powered devices, and these have some interesting potential advantages over Intel’s Xeon server processors. The next-generation ARM chips will have some new features that are particularly useful for HPC workloads, but we can start testing the current generation of chips and get a pretty good idea of how HPC applications will perform.”
The ARM1 test bed system, which was built by Cray, went online in September 2016 and is currently accepting applications from researchers in the DOE community. Among those interested in the system are experts who work on HPC tools and libraries and with compilers, which translate programming instructions into intelligible directions for the computer. Because ARM processors have yet to be used in any of the OLCF’s current systems, ARM1 will give internal users a chance to assess the state of the ARM ecosystem.
Oscar Hernandez, tools developer in the OLCF Computer Science Research Group, was granted access to the ARM1 test bed system to explore potential issues and gain a better understanding of how ARM might work in an HPC context.
“Getting early access to an ARM-based system is important to understand what’s available and what’s not in its HPC software stack and how ready it is for our applications today,” Hernandez said.
Wael Elwasif, computer scientist in the OLCF Computer Science Research Group, hopes to use the ARM1 system to investigate new possibilities and examine high-level programming models that may help applications from different architectures port to and use such a system.
“Developers want to run their applications on all available high-performance platforms,” Elwasif said. “If we can run the same applications and programming model that we use on leadership-class platforms such as Titan on this new test bed, ARM could have potential as an exascale computing architecture.”
Miller said ARM1 ultimately will benefit the OLCF because of its potential as a candidate for future extreme-scale system architectures.
“ARM definitely has advantages,” he said. “For one, the architecture allows designs with more memory bandwidth than current x86 designs. And although it’s known for low-power chips for mobile devices, it’s possible to build a high-performance ARM CPU, as well.”
Another advantage, Miller said, is that ARM Holdings licenses ARM technology to different chip vendors, enabling them to incorporate it into their own designs. Companies can design their own ARM chips that are optimized for HPC workloads. An ARM chip designed specifically for the HPC community would be significantly different from one designed for use in a smartphone, for example.
Some organizations have already announced plans to use ARM in future architectures. Fujitsu has announced that Japan’s Post-K machine will be ARM-based and will use ARM’s recently added Scalable Vector Extensions (SVE). SVE provides support for vectors—groups of values that a computer can use to perform multiple simultaneous operations—of up to 2,048 bits, making it an even better candidate for HPC systems because longer vectors can help support increased parallelism.
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